Method and apparatus for division employing table-lookup and functional iteration

ABSTRACT

Disclosed is a divide method and a divide apparatus for use in a data processing system. A given dividend, No, and a given divisor, Do, are used to calculate a quotient Q. The quotient Q consists of the quotient bytes Q(O), Q(l),...,Q(i), Q(i+l),..., Q(n-l). The quotient bytes Q(i) are formed in successive iterations of the equation

United States Patent Amdahl et al.

[ Aug. 6, 1974 METHOD AND APPARATUS FOR DIVISION EMPLOYING TABLE-LOOKUP AND FUNCTIONAL ITERATION [75] Inventors: Gene M. Amdahl, Saratoga; Michael R. Clements, Santa Clara, both of Calif.

[73] Assignee: Amdahl Corporation, Sunnyvale,

Calif.

[22] Filed: Oct. 30, 1972 [21] Appl. No.: 302,223

[52] US. Cl. 235/164 [51] Int. Cl. G06f 7/52 [58] Field of Search 235/164, 159, 160, 156

[56] References Cited UNITED STATES PATENTS 3,591,787 7/1971 Freiman 235/164 3,633,018 l/1972 Huei Ling 235/164 3,648,038 3/1972 Sierra 235/164 OTHER PUBLICATIONS M. J. Flynn, On Division by Functional Interation, IEEE Trans. on Computers, Vol. Cl9,'No. 8, Aug. 70, PP 202-206.

Primary ExaminerCharles E. Atkinson Assistant Examiner-David H. Malzahn Attorney, Agent, or FirmFlehr, Hohbach, Test, Albritton & Herbert [57] ABSTRACT Disclosed is a divide method and a divide apparatus for use in a data processing system. A given dividend, No, and a given divisor, D0, are used to calculate a quotient Q. The quotient Q consists of the quotient bytes Q(O), Q(l),...,Q(i), Q(i+l),...,Q(nl). The quotient bytes Q(i) are formed in successive iterations of the equation 7 Claims, 3 Drawing Figures .22 I I24 I I ,2: H i i 1 21-256 i-Pra ,2

I I I I I I I Err! I I I I .I

METHOD AND APPARATUS FOR DIVISION EMPLOYING TABLE-LOOKUP AND FUNCTIONAL ITERATION CROSS REFERENCE TO RELATED APPLICATIONS DATA PROCESSING SYSTEM, Ser. No. 302,221, filed Oct. 30, 1972, invented by Gene M. Amdahl and Glenn D. Grant and assigned to AMDAI-IL CORPO- RATION.

BACKGROUND OF THE INVENTION The present inventionrelates to the field of data processing systems and specifically to the field of dividers and methods for dividing within data processing systems.

Prior art data processing systems usually include within their instruction set, instructions which require divisions of numbers using either fixed point or floating point algorithms.

Prior art methods and apparatus for executing divide instructions typically employ combinations of adders and other functional units rather than employing a single dedicated divide apparatus. The quotient Q is calculated from a given divisor Do and a given dividend No using an iterative process or algorithm requiring,

many cycles of the system.

In order to simplify the calculations, approximations of the given dividend and given divisor are frequently employed so that inaccuracies, within predetermined limits, may be introduced into the quotient. In prior art iteration sequences, the iteration approximations cause intermediate results which are both positive and negative thereby requiring both addition and subtraction steps in order that the quotient be accurately formed. While such iteration sequences produce acceptable results, the requirement of having to keep track of positive and negative remainders is undesirably complex and may necessitate additional circuitry which adds to the expense of the data processing system.

SUMMARY OF THE INVENTION The present invention is a method of division and divider apparatus for use in a data processing system. A given dividend No and a given divisor D are used to calculate a quotient Q. The quotient 0 consists of the quotient bytes Q(O), Q(l),...,(Q(i), Q(i-H), ...,Q(nl).

Those quotient bytes Q(i) after Q(O) are formed in successive iterations of the following general form:

where (dp) is the iteration multiplier and r(i) is the i" truncated remainder resulting after truncating Q(i) from the previous iterations. The iteration multiplier (dp) equals l-D(Dp) where (Dp) is an approximate reciprocal divisor and where D is the binary normalized Do. For quotient bytes Q(i) each of x binary bits, (Dp) does not differ from D by more than 1 part in 2. The approximate reciprocal divisor (Dp) and the iteration multiplier (dp) are determined during an initial calculation using a table-lockup approximate reciprocal divisor (Dt). The table-lockup approximation (Dr) is selected so that (Dr) does not differ from D by more than one part in 2 Through the initial calculations, the first quotient byte Q(O) is produced and the approximate reciprocal divisor (Dp) is derived from the approximate reciprocal divisor (D2)".

Because the approximate reciprocal divisors (Dp) and (Dt) are less than the exact reciprocal of the divi sor D, the remainders, r(i), are always less than the remainders which would be formed if the exact reciprocal divisor Do were employed. Accordingly, the addition of Q(i) (dp) to r(i) is always of the same sign.

In accordance with the above summary, the present invention achieves the object of accurately forming a quotient Q from a given divisor Do and a given dividend No by an iterative process of forming quotient bytes by adding a truncated remainder to the product of the last quotient byte and an iterative multiplier (dp) to fonn the next quotient byte and the next remainder.

Additional objects and features of the invention will appear from the following description in which the preferred embodiments of the invention have been set forth in detail in conjunction with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 depicts a block diagram of a basic environmental system suitable for employing the divide method and apparatus of the present invention.

FIG. 2 depicts a flow chart of the method steps of the present invention.

FIG. 3 depicts a schematic representation of the data paths and apparatus associated with the execution unit of the system of FIG. 1 and wherein division instructions are executed.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Overall System In FIG. 1, a basic environmental processing system is shown which is suitable for employing the divider and division method of the present invention. Briefly, that system includes a main store 2, a storage control unit 4, instruction unit 8, an execution unit 10, a channel unit 6 with associated I/O, and a console 12. In accordance with well known principles, the data processing system of FIG. 1 operates under control of a stored program of instructions. Typically, instructions and the data upon which the instructions operate are introduced from the [/0 equipment via the channel unit 6 through the storage control unit 4 into the main store 2. From the main store 2, instructions are fetched by the instruction unit 8 through the storage control 4, and are decoded to control the execution of instructions. Execution unit 10 executes instructions decoded in the instruction unit 8 and operates upon data communicated to the execution unit from the appropriate places in the system. Execution Unit In FIG. 3, the execution unit 10 of the system of FIG. 1 is shown in further detail. The execution unit has a plurality of functional units including a multiplier 19, an adder 18, a shifter 30, a byte adder 32 and a LUCK unit 20 for performing logical and comparison operations. Those functional units are typically implemented using apparatus and techniques well known in the data processing field. In addition to the functional units, the execution unit 10 includes a plurality of registers which function to store, to ingate and to outgate data from the various functional units in controlled steps pursuant to executing the programmed instructions of the data processing system of FIG. 1. Specifically, those registers are an I register 22, a 1H register 24, a 1L register 28,

a 2H register 25, a 2L register 29, a B register 23, a G register 36, an S register 35, a C register 37, an A register 39 and an R register 34.

Additionally, the E unit also includes a control 27 which controls in a conventional manner the ingating, outgating and other timing associated with execution unit 10.

The execution unit 10 also includes a table-lockup unit 26. The table-lookup unit 26 receives as an input the higher order divisor bits when a divide instruction is being performed and provides as an output an approximate divisor reciprocal for use in establishing an iteration multiplier. The table-lookup unit includes conventional logic decoding circuitry further described hereinafter.

While the general nature and operation of an execution unit like that in FIG. 10 is well known, certain specific features are explained in further detail in connection with the divide algorithm of the present invention.

Divide Algorithm Background In accordance with the present invention, an iterative process is executed to form a quotient Q from a given dividend N and a given divisor D. In general, N/D identically equals a quotient Q with some exact remainder R as follows:

The quotient Q can be expressed as an ordered sequence of bytes Q(i) which are explicitly Q(O), Q( Q( Q( ---,Q(

Each of the Q(i) bytes may be determined by obtaining the Q(i+l) byte from the previous remainder R(i) as follows:

Further, each term in Eq. 3 is multiplied by (Dp) as follows:

p) Q( U P)" P)' Using the form of Eq. 2 in Eq. 4 where (Dp) equals ldp)D' and letting the asterisk indicate possibly inexact quantities resulting from introducing the approximation (Dp) rather than using only the exact value D yields:

With proper selection of (rip) and therefore of (dp) in Eq. 5, Q* (i+1) equals Q(i+l) and Q(i+2) equals Q*(i+2) so that Eq. 5 becomes:

Rewriting Eq. 6 letting i (i-l) yields:

p) is the remaining low order bits, r(i+l in which case Eq. 7 becomes,

In. Eq. 8 the initial values, r(0) and Q(o) for r (i) and Q(i) are established by multiplying the dividend N by an appropriately chosen reciprocal divisor (Dp). The appropriate selection of the approximate reciprocal divisor (Dp) besides establishing r(0) and Q(o) establishes the value for the iteration multiplier (dp).

Several factors are considered in establishing the iteration multiplier (dp). First, the value of (Dp)" must be accurate enough to insure that the possibly inexact byte Q*(i+2) is in fact identically equal to the exact byte Q(i+2) as previously discussed in connection with Eq. 5 above. Specifically, where the bytes Q(i) are eight bits in binary notation, each byte represents a value up to 2 Accordingly, in order that the high order byte Q*(i+2) in Eq. 2 not be affected by inaccuracy the approximate divisor (Dp) must differ from the actual divisor D by less than one part in 2 that is, (Dp) should differ from D by less than 2 and for x bit bytes (Dp) should differ by less than 2x.

Another factor to consider in establishing the iteration multiplier (a'p) is the technique of and apparatus for establishing the approximate reciprocal divisor (Dp) Still further, the capacity of the data processing system for handling multiplicands of limited bit length must be considered.

In accordance with the present invention and in view of the above factors, (Dp) is obtained by an initial calculation. First, a table-lookup unit is addressed by the seven high-order bits of the normalized divisor D to provide a table-lockup approximate reciprocal divisor (D1)". The table is constructed such that (Dr) differs from D by amounts not greater than 2' The tablelookup reciprocal divisor (Dt) is used to calculate the approximate reciprocal divisor (Dp)". The calculation is carried out so as to insure that (Dp) differs from D by amounts less than T.

In converting the table-lookup reciprocal divisor (Dt) to (Dp), (D2) is first multiplied by D forming the quantity (1-dt) as follows: I

Next, the twos complement of the quantity (l-dt) is taken to form the quantity 1 (dt) as follows:

Finally, the quantity [l+(dt)] is multiplied by (Dt) as to produce (D1)) follows:

Because the divisor D is binary normalized, that is, all high-order Os are truncated, the value of D is less than I and is greater than or equal to one-half. Also, (Dt) does not differ from D by more than 2'. Accordingly, the product of (Dt) D of Eq. is less than (l2 so that (dt) in Eq. 9 is less than 2 From Eq. 9 it is clear that (Dt)" is less than (1-dr). Using (Dt) in Eq. 12 as less than (1-dt) establishes (Dp) as less than the product of l+dt and l-dt as follows:

The product [l-l-dt] [l-a't] of course yeilds the product l(dr) Since (dt) was established as less than 2' (dt) in Eq. (14) is less than 2 In accordance with Eq. 14, (Dp) is established as differing from D by a value less than 2 as desired. Using the established value of (Dp) the iteration multiplier (dp) is formed by multiplying (Dp) by D and forming the ones complement of the product. Having thereby established the iteration multiplier dp, Eq. 8 is repeatedly iterated to establish the Q (i) quotient bytes in accordance with the method of the present invention which is now more explicitly described. Divide Method The divide method of the present invention operates upon a given divisor D0 and a given dividend No to calculate a quotient Q in accordance with the following steps.

Step 1. Binary normalize Do by truncating y highorder Os to form D and shift N0 Y bits to form N.

Step 2. Use high order bits of D to address tablelookup logic to obtain (Dt)" where l/D 2 l/(Dt) and therefore (Dt) 2 D and D/(Dt) 1.

Step 3. Multiply (Dt) by D:

(Dt)" (D) 1-dr Exp. I

Step 4. Form twos complement of l(dt)]:

[l-(dt)]" 2-[l-(dt)]=[1+(dl)l Exp. ll

(D12) (Dt) l.OO---0 D/(Dp) D/(Dt) Exp. I"

Step 6. Multiply (Dp) by D:

( M P)l (dp) [l(Dp)"( )l Exp. IV

Step 7. Form ones complement of [l(dp)] pll' pfl P) Exp. v

Step 8. Multiply (Dp) by N:

( PYU Q( Exp. VI

Step 9. Multiply Q(O) by (dp) and add result to r(O) Q( P)+ Q( Exp. VII

Step [0. Multiply Q(i) by (dp) and add result to r(i) for i l,...,(n-l [Q(i)](dp)+r(i) Q(i+l r(i+l) Exp. Vlll where:

N0 givendividend N normalized No shifted y-bits D0 given divisor D binary normalized Do, truncated y-bits v Q calculated quotient having Q(i) bytes Q(O),

Q( Q( ),Q( ,Q(" (Dt) table lookup approximate reciprocal divisor (dt) l-D(Dt) initial multiplier (Dp)' calculated approximate reciprocal divisor (dp) l---D(Dp) iterative multiplier Q(i) i" calculated byte of the quotient Q r(i) i'" truncated remainder formed by truncating Q( from Q( i= 0, l, 2,..., (n-l) iterative steps n number of quotient bytes, 4 for single word accuracy and 8 for double word Note that the method outlined in the above steps is consistent with the equations and discussion in the above Divide Algorithm Background. Specifically, the iteration of Exp. VIII is identical to that previously discussed in connection with Eq. 8. Similarly,- the formation of the iteration multiplier (dp) of Exp. i's' accordance with the discussion of Eqs. 9 through Because the approximate reciprocal divisor (Up) is greater than the reciprocal divisor D, each new remainder r(i+l) is smaller than the remainder which would be obtained if the exact divisor D were employed rather than the approximate divisor Dp. In each instance, the addition of the product (dp) and Q(i) is necessary to increase the quantity r(i) in order to insure that the next quotient byte Q(i+l is without error. Because r(i+l) is always generated smaller than the actual remainder, addition is always required; therefore,

it is not necessary to keep track of the sign of the remainder. Divide Apparatus The execution unit of the system of FIG. 1 carries out the divide method depicted in FIG. 2 using the apparatus of FIG. 3. Referring to FIG. 3, the execution unit executes a divide instruction by fetching through the LUCK unit the dividend No to the 1H and IL registers 24 and 28 and the divisor D0 to the 2H register 25.

In Step 1, the dividend No is transferred, by conventional means under control of control unit 27, from the 1H and IL registers to the 2H and 2L registers while the divisor Do is transferred from the 2H register to the 2L register to the IL register through the LUCK unit 20 where the number, y, of high order 0s is counted, and placed in the SAR register 38 in the shifter 30. The divisor Do is transferred from the IL register through the shifter 30 where it is shifted y bits to form the normalized divisor D which is placed in the IL register. Simultaneously, with placing the divisor D in the IL register, the seven high order bits of D are placed in the 1H register.

In Step 2, the high order bits of D from the 1H register are gated as an input to the table lookup unit"26 which produces as an output the approximate divisor (Dt) which is stored in the I register 22.

In Step 3, the approximate divisor (Dt) is multiplied by D by transferring D from the IL register and (D!) from the I register through the multiplier placing the product (la't) in the 2H and 2L registers via the S and C registers 35 and 37 and the adder 18. That result is then truncated to 32 bits leaving the results in the 2H register.

In Step 4, the twos complement of the contents of the 2H register are formed by passing that value through the adder l8 and placing the result l-l-(dt)] in the IL register. Simultaneously therewith, the divisor D is transferred from the IL register to the 2H register.

In Step 5, l-I-dt) from the IL register and D from the 2H register are gated to the multiplier and the product of those terms is placed in the 1H and IL registers thereby forming the approximate reciprocal divisor (D1)). From the 1H and IL registers, the approximate divisor is transferred to the I register truncating the lower order bits.

In Step 6, (Dp) from the I register and D from the IL register are gated to the multiplier 19 and the product l-(dp)] after passing through the S and C registers and adder 18 is placed in the A register 39.

In Step 7, the contents of the A register are gated through the adder 18 to form the ones complement and form the iteration multiplier (dp) which is placed in the R register.

In Step 8, concurrently during the performance of Step 7, the product of (D1)) and N is formed placing the results in the IL, 2H, 2L and A registers for the remainder portion r(0) and the high order byte Q(O) in the I register.

In Step 9, Q(O) from the I register is multiplied by the iteration multiplier (dp) from the R register via the 1H register via multiplier 19 while the r(0) remainder is simultaneously gated from the A register to the multiplier 19. The result of the simultaneous multiplication and addition according to Exp. VII above places the remainder r(1) in the A register and the new quotient in the 2L register in preparation for the next step.

In Step 10, the Q( 1) byte from the I register and the r( l) remainder in the A register are multiplied by the iteration multiplier (dp) and added in accordance with Exp. VIII above placing the new byte Q(2) in the I register while forming the new remainder in the A register and accumulating the bytes Q(O), Q(l) and Q( 2) in the 2L register.

Thereafter, the iteration in accordance with Exp. VIII continues, gating the most recently formed byte from the I register to the multiplier along with the iteration multiplier (dp) from the 1H register and the previously obtained remainder from the A register. Accumulation continues in the 2L register until the divide algorithm is completed.

The table lookup unit 26 in FIG. 3 in one preferred embodiment is a logical decoding apparatus which is addressed by the seven high order bits of the divisor D. While a logical implementation is preferred, the information can alternatively be stored in main store or other storage areas in the data processing system. For example, each of the locations defined by the seven high order bits of the divisor D can be loaded with the correct reciprocal divisor determined in accordance with the following algorithm.

(Di) the output from the table lookup unit D the divisor input to the table lookup unit 7 truncation to seven bits For a specific example of how the above algorithm is employed in forming the information used to load the table with the desired approximate reciprocal divisors, a typical divisor D is selected and expressed in binary notation as 0.100001 10. The quantity DZ is 0.1000011 which is truncated value of D to seven significant bits. The quantity (D$ 7+l) is equal to 0.1000100. The value of [1/(Dfi-l-1)] is 1.11100001. The quantity [l/(D/+l)]1 is 1.111000.

In summary, for a divisor D equal to 0.10000110 the table lookup approximate reciprocal divisor (MT is 1.111000.

Since the approximate reciprocal divisors (D2) and (Dp) are less than the actual reciprocal divisor D, the algebraic additions of Expressions VII and VIII above were always the same sign and more specifically were always a positive sign. Alternatively, the present invention may be implemented by selecting (Dt) and (D greater than D. When the approximate reciprocal divisors are selected, greater, than the algebraic additions of Expressions VII and VIII are still always of the same sign, but that sign is negative.

Specific Divide Example As a specific example of the divide method of the present invention, the dividend No and the divisor D0 are given in hexidecimal format as follows:

N 0123456789ABCDEF D0 02468ADO The quotient Q, in hexadecimal format, calculated from the above dividend and divisor is as follows:

Q 0.7FFFFFCC The steps performed in calculating the above quotient Q are summarized in the following TABLE I.

TABLE I Step 1 Since for Do the leading high order'bits (ignoring the first bit which is a sign bit) are 01(Hex) which equals 0000000 1 (binary), D0 has six leading Os so Do and N0 are shifted left six bits to form:

D 0.91A2B400(Hex) N =0.48Dl59E26AF37BCO(l-lex) Step 2 The seven high order bits of D, where 91(Hex) equals 1001000l(binary), are 1001000 and those seven bits are used to address the table lookup to obtaln:

(Dt)' l.11000000(binary) l.CO(HeX) Step 3 Multiply D which is equal to 0.91A2B400(l-lex) by (D1) which is equal to l.CO(l-lex): (D1)"D [l-(dt)] O..FEDCBBOOOO Step 4 Twos complement [l-(dt)]: [l(dl)]" [l+(dt)] 1.0123450000 Step 5 ,Multiply [l+(dt)] by (DU [l-l-(a t)](Dt) (Dp) LCIFDBSCOOOO Step 6 Multiply (Dp)' by D:

D(Dp)' [l-(dp)] 0.FFFEB49AOF6 Step 7 r Ones complement [l(dp)]: [l-(dp)]' (dp) 0.00014B65FOA Step 8 Multiply (Dp)' by N: (Dp)"N Q(O), r(O) 0.7FFF5A194BA Multiply Q(O) by (dp) and add to r(0): [Q( P)+ Q( 1 Q( r( l) .FE80DDF Step 10 Multiply Q( l) by (dp) and add to r( l Q( FF r(2) .CAF87A Step 1 1 Multiply Q(2) by (dp) and add to r(2); Q( P)+ Q( Q(3) .CC r(3) .4295 The quotient Q equal to .7FFFFFCC can be checked by multiplying that value of Q times the original divisor D0 and adding the remainder r(3) to the product and the answer obtained therefrom will be the original dividend No. When adding the remainder r(3) to the prod- 10 not, it must be appropriately weighted by adding eight leading Os to form .000000004295. An alternative technique for checking the division is to multiply the quotient Q by the normalized divisor D and adding the remainder r(3) appropriately shifted to the product. The appropriate shift is six leading Os corresponding to the original binary normalization shift of Do. When appropriately shifted, the remainder which is added is .0000002F.

While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention. 7

We claim:

1. A data processing system storing a dividend N and a divisor D which are operated upon to form a quotient Q, where Q includes n quotient bytes Q(O), Q(l),..., Q(i), Q(i+l),..., Q(n-l said system comprising,

a first unit for concurrently adding and multiplying operands,

a second unit for adding, for ones complementing and for twos complementing operands, a shifter unit for shifting operands, a plurality of registers for storing operands, including said dividend N and said divisor D, control means for controlling the processing of operands,

a table-lookup unit for storing a plurality of first approximate reciprocal divisors; means, responsive to said control means for gating high-order bits of said divisor D from said registers to said table-lookup unit to gate a corresponding one, (Dt) of said first approximate reciprocal divisors into said registers; means, responsive to said control means, for gating the approximate reciprocal divisor (Dt) and the divisor D from said registers to said first unit to form the product D(Dt)' which equals [l-(dt)] where (dt) is an initial multiplier, means, responsive to said control means, connecting said first unit to said registers for storing [1-(dt)] in said registers;

means, responsive to said control means, for gating [l-(dt)] from said registers to said second unit for twos complementing [1-(dt)] to form [l+(dt)],

means, responsive to said control means, connecting said second unit to said registers for storing [1+(dt)] in said registers;

means, responsive to said control means, for gating [1+(dt)] and the approximate reciprocal divisor (Dt) from said registers to said first unit to form the product [l+(dt)](Dt) which equals a second approximate reciprocal divisor (Dp) means, responsive to said control means, connecting said first unit to said registers for storing (D1)) in said registers.

2. The apparatus of claim 1 including,

means, responsive to said control means, for gating the approximate reciprocal divisor (Dp)' and the divisor D from said registers to said first unit to form the product D(Dp) which equals [l-(dp)] where (dp) is an iterative multiplier;

means, responsive to said control means, connecting said first unit to said registers for storing [l-(dP)] in said registers,

means, responsive to said control means, for gating [l-(dp)] from said registers to said second unit to form the one s complement of [1-(dp)] equal to the iterative multiplier (dp); and means, responsive to said control means, connecting said second unit to said registers for storing the iterative multiplier (dp) in said registers. 3. The system of claim 2 in which N is a given dividend stored in said registers and D0 is a given divisor stored in said registers, said system including,

means, responsive to said control means, connecting said registers to said shifting unit for binary normalizing said divisor Do by shifting y bits to truncate all high-order Os thereby forming said divisor D,

means, responsive to said control means, connecting said shifter unit to said registers for storing said divisor D in said registers,

means, responsive, to said control means, for gating said dividend No'to said shifter unit for shifting the dividend N0 y bits thereby forming said dividend N,

means, responsiveto said control means, connecting said shifter unit to said registers for storing said dividend N in said registers.

4. The apparatus of claim 2 including,

means, responsive to said control means, for gating (Dp) and N to said first unit for multiplying (Dp) by N to form Q(O), r(O), where r(O) is the 0" truncated remainder of the truncated remainders r(i),

means, responsive to said control means, connecting said first unit to said registers for storing Q(O), r(O) in said registers,

means, responsive to said control means, for gating (dp), Q(O) and r(O) to said first unit for multiplying (dp) by Q(O) and adding the product to r(O) to' form the term Q( l r( l) where r( l) is the 1" truncated remainder of the truncated remainders r(i),

means, responsive to said control means, connecting said first unit to said register means for storing Q( l r( l) in said registers, means, responsive to said control means, for iteratively gating (dp), Q(i), and r(i) from said registers to said first unit for iteratively multiplying (dp) by Q(i) and adding the product to r(i) to form Q(i+l r(i+l) for all values ofi from l to (nl), means, responsive to said control means, connecting to said first unit to said registers for iteratively storing Q(i+l r(i+l) in said registers for all values of i from I to (n-l 5. A data processing system storing a dividend N and a divisor D which are operated upon to form a quotient Q where Q includes n non-overlapping quotient bytes Q(O), Q( l ),...,Q(i), Q(i+l ),...,Q(nl where each byte includes x binary bits, said system comprising,

a first unit for concurrently adding and multiplying operands, a second unit for adding, for ones complementing and for twos complementing operands, a shifter unit for shifting operands, a plurality of registers for storing operands, including said dividend N and said divisor D, control means for controlling the processing of operands, a table-lookup unit for storing a plurality of first approximate reciprocal divisors of the form (Dt) where (Dt) does not differ from D by more than 2-(1'12).

means, responsive to said control means, for gating high-order bits of said divisor D from said registers to address said table-lookup unit to access a corresponding one, (Dt) of said first approxiamte reciprocal divisors,

means, responsive to said control means, connecting said table-lookup unit to said registers for storing said reciprocal divisor (Dr); in said registers,

means, responsive to said control means, for gating said reciprocal divisor (Dt); and the divisor D from said registers to said first unit to form the j product D(Dt) which equals [l(dt)] where (dt) is an initial multiplier,

means, responsive to said control means, connecting said first unit to said registers for storing [l(dt)] in said registers;

means, responsive to said control means, for gating [l(dt)] from said registers to said second unit for twos complementing [l(dt)] to form [1+(dt)],

means, responsive to said control means, connecting said second unit to said registers for storing [1+(dr)] in said registers;

means, responsive to said control means, for gating [l-Ha't)] and the approximate reciprocal divisor (Dt) from said registers to said first unit to form the product [1+(dt)] (Dt) which equals a second approximate reciprocal divisor (Dp) where (Dp) does not differ from D by more than 2 means, responsive to said control means, connecting said first unit to said registers for storing (Dp) in said registers.

6. A method of division in a data processing system storing a dividend N and a divisor D which are operated upon to form a quotient Q where Q includes n nonoverlapping quotient bytes Q(O), Q(l),...,Q(i), Q(i+l Q(n-l) and where each byte includes x binary bits; said system having a first unit for concurrently adding and multiplying operands; having a sec- 0nd unit for adding, for ones complementing and two s complementing operands; having a plurality of registers for storing operands including said dividend N and said divisor D; having control means for controlling the processing of operands; having a table-lockup unit for storing a plurality of first reciprocal divisors of the form (Dt) where (Dt) does not differ from D by more 2' the steps comprising,

addressing said table-lookup unit with the high-order bits of D to access a corresponding one, (DO of said first approximate reciprocal divisors,

storing (Dt), in said register means,

gating (Dr); and D to said first unit,

multiplying (Dt); and D in said first unit to form [l(dt)] where (dt) is an initial multiplier, storing [l-(dt)] in said register means, gating [l-(dr)] to said second unit, twos complementing [l(dt)] in said second unit to form MO],

storing [bl-(dt)] in said register means, gating [l-{dtH and (Dr); to said first unit,

multiplying l-l-(dt)] and (Dt) in said first unit to fonn a calculated reciprocal divisor (Dp) whereby (Dp) does not differ from D by greater than 2 storing (Dp) in said register means.

13 7. The method of claim 6 including the steps, gating (D1)) and D to said first unit,

gating Q(O), (dp), and r(0) to said first unit,

multiplying Q(O) and (dp) and adding r(O) to the product in said first unit to form Q( l r( l storing Q( 1 r( 1) in said registers,

iteratively gating (dp), Q(i), and r(i from said registers to said first unit for all values of i from 1 to iteratively multiplying (dp) by Q(i) in said first unit to form the product (dp)Q(i) and adding said product (dp)Q(i) to r(i) in said first unit to form Q(i+l r(i+1) for all values ofi from 1. to (n-l all values of i from 1 to (n-l). 

1. A data processing system storing a dividend N and a divisor D which are operated upon to form a quotient Q, where Q includes n quotient bytes Q(0), Q(1),..., Q(i), Q(i+1),..., Q(n-1), said system comprising, a first unit for concurrently adding and multiplying operands, a second unit for adding, for one''s complementing and for two''s complementing operands, a shifter unit for shifting operands, a plurality of registers for storing operands, including said dividend N and said divisor D, control means for controlling the processing of operands, a table-lookup unit for storing a plurality of first approximate reciprocal divisors; means, responsive to said control means for gating high-order bits of said divisor D from said registers to said table-lookup unit to gate a corresponding one, (Dt) 1, of said first approximate reciprocal divisors into said registers; means, responsive to said control means, for gating the approximate recIprocal divisor (Dt) 1 and the divisor D from said registers to said first unit to form the product D(Dt) 1 which equals (1-(dt)) where (dt) is an initial multiplier, means, responsive to said control means, connecting said first unit to said registers for storing (1-(dt)) in said registers; means, responsive to said control means, for gating (1-(dt)) from said registers to said second unit for two''s complementing (1-(dt)) to form (1+(dt)), means, responsive to said control means, connecting said second unit to said registers for storing (1+(dt)) in said registers; means, responsive to said control means, for gating (1+(dt)) and the approximate reciprocal divisor (Dt) 1 from said registers to said first unit to form the product (1+(dt))(Dt) 1 which equals a second approximate reciprocal divisor (Dp)116 1; means, responsive to said control means, connecting said first unit to said registers for storing (Dp) 1 in said registers.
 2. The apparatus of claim 1 including, means, responsive to said control means, for gating the approximate reciprocal divisor (Dp) 1 and the divisor D from said registers to said first unit to form the product D(Dp) 1 which equals (1-(dp)) where (dp) is an iterative multiplier; means, responsive to said control means, connecting said first unit to said registers for storing (1-(dp)) in said registers, means, responsive to said control means, for gating (1-(dp)) from said registers to said second unit to form the one''s complement of (1-(dp)) equal to the iterative multiplier (dp); and means, responsive to said control means, connecting said second unit to said registers for storing the iterative multiplier (dp) in said registers.
 3. The system of claim 2 in which No is a given dividend stored in said registers and Do is a given divisor stored in said registers, said system including, means, responsive to said control means, connecting said registers to said shifting unit for binary normalizing said divisor Do by shifting y bits to truncate all high-order 0''s thereby forming said divisor D, means, responsive to said control means, connecting said shifter unit to said registers for storing said divisor D in said registers, means, responsive, to said control means, for gating said dividend No to said shifter unit for shifting the dividend No y bits thereby forming said dividend N, means, responsive to said control means, connecting said shifter unit to said registers for storing said dividend N in said registers.
 4. The apparatus of claim 2 including, means, responsive to said control means, for gating (Dp) 1 and N to said first unit for multiplying (Dp) 1 by N to form Q(0), r(0), where r(0) is the 0th truncated remainder of the truncated remainders r(i), means, responsive to said control means, connecting said first unit to said registers for storing Q(0), r(0) in said registers, means, responsive to said control means, for gating (dp), Q(0) and r(0) to said first unit for multiplying (dp) by Q(0) and adding the product to r(0) to form the term Q(1), r(1) where r(1) is the 1st truncated remainder of the truncated remainders r(i), means, responsive to said control means, connecting said first unit to Said register means for storing Q(1), r(1) in said registers, means, responsive to said control means, for iteratively gating (dp), Q(i), and r(i) from said registers to said first unit for iteratively multiplying (dp) by Q(i) and adding the product to r(i) to form Q(i+1), r(i+1) for all values of i from 1 to (n-1), means, responsive to said control means, connecting to said first unit to said registers for iteratively storing Q(i+1), r(i+1) in said registers for all values of i from 1 to (n-1).
 5. A data processing system storing a dividend N and a divisor D which are operated upon to form a quotient Q where Q includes n non-overlapping quotient bytes Q(0), Q(1),...,Q(i), Q(i+1), ...,Q(n-1), where each byte includes x binary bits, said system comprising, a first unit for concurrently adding and multiplying operands, a second unit for adding, for one''s complementing and for two''s complementing operands, a shifter unit for shifting operands, a plurality of registers for storing operands, including said dividend N and said divisor D, control means for controlling the processing of operands, a table-lookup unit for storing a plurality of first approximate reciprocal divisors of the form (Dt) 1 where (Dt) does not differ from D by more than 2 (x/2), means, responsive to said control means, for gating high-order bits of said divisor D from said registers to address said table-lookup unit to access a corresponding one, (Dt)c 1, of said first approxiamte reciprocal divisors, means, responsive to said control means, connecting said table-lookup unit to said registers for storing said reciprocal divisor (Dt)c 1 in said registers, means, responsive to said control means, for gating said reciprocal divisor (Dt)c 1 and the divisor D from said registers to said first unit to form the product D(Dt) 1 which equals (1-(dt)) where (dt) is an initial multiplier, means, responsive to said control means, connecting said first unit to said registers for storing (1-(dt)) in said registers; means, responsive to said control means, for gating (1-(dt)) from said registers to said second unit for two''s complementing (1-(dt)) to form (1+(dt)), means, responsive to said control means, connecting said second unit to said registers for storing (1+(dt)) in said registers; means, responsive to said control means, for gating (1+(dt)) and the approximate reciprocal divisor (Dt) 1 from said registers to said first unit to form the product (1+ (dt)) (Dt) 1 which equals a second approximate reciprocal divisor (Dp) 1 where (Dp) does not differ from D by more than 2 x, means, responsive to said control means, connecting said first unit to said registers for storing (Dp) 1 in said registers.
 6. A method of division in a data processing system storing a dividend N and a divisor D which are operated upon to form a quotient Q where Q includes n non-overlapping quotient bytes Q(O), Q(l),...,Q(i), Q(i+1),..., Q(n-1) and where each byte includes x binary bits; said system having a first unit for concurrently adding and multiplying operAnds; having a second unit for adding, for one''s complementing and two''s complementing operands; having a plurality of registers for storing operands including said dividend N and said divisor D; having control means for controlling the processing of operands; having a table-lookup unit for storing a plurality of first reciprocal divisors of the form (Dt) 1 where (Dt) does not differ from D by more 2 (x/2), the steps comprising, addressing said table-lookup unit with the high-order bits of D to access a corresponding one, (Dt)c 1, of said first approximate reciprocal divisors, storing (Dt)c 1 in said register means, gating (Dt)c 1 and D to said first unit, multiplying (Dt)c 1 and D in said first unit to form (1-(dt)) where (dt) is an initial multiplier, storing (1-(dt)) in said register means, gating (1-(dt)) to said second unit, two''s complementing (1-(dt)) in said second unit to form (1+(dt)), storing (1+(dt)) in said register means, gating (1-(dt)) and (Dt)c 1 to said first unit, multiplying (1+(dt)) and (Dt)c 1 in said first unit to form a calculated reciprocal divisor (Dp) 1 whereby (Dp) does not differ from D by greater than 2 x, storing (Dp) 1 in said register means.
 7. The method of claim 6 including the steps, gating (Dp) 1 and D to said first unit, multiplying (Dp) 1 and D in said first unit to form (1-(dp)), storing (1-(dp)) in said register means, gating (1-(dp)) from said registers to said second unit, one''s complementing (1-(dp)) in said first unit to form (dp) where (dp) is an iterative multiplier, storing (dp) in said registers, gating (Dp) 1 and N to said first unit, multiplying (Dp) 1 and N in said first unit to form Q(0), r(0) where r(0) is a 0th truncated remainder of the truncated remainder r(i), storing Q(0), r(0) in said registers, gating Q(0), (dp), and r(0) to said first unit, multiplying Q(0) and (dp) and adding r(0) to the product in said first unit to form Q(1), r(1), storing Q(1), r(1) in said registers, iteratively gating (dp), Q(i), and r(i ) from said registers to said first unit for all values of i from 1 to (n-1), iteratively multiplying (dp) by Q(i) in said first unit to form the product (dp)Q(i) and adding said product (dp)Q(i) to r(i) in said first unit to form Q(i+1), r(i+1) for all values of i from 1 to (n-1), iteratively storing Q(i+1), r(i+1) in said registers for all values of i from 1 to (n-1). 